Joel Auernheimer

Summary

• Proven engineer with well-rounded competencies within computer science, electrical engineering, project management, and people management
• Excellent communication skills (verbal and written)

Industry Recognitions and Community Leadership:

• Young Engineer of the Year (IEEE Phoenix Chapter, 2008)
• Senior Member of the IEEE (2009)
• The Phoenix Symphony Chorus (including board service)

Education

• Master of Science in Computer Science from Arizona State University, May 2013 (4.0 GPA).
• Master of Science in Electrical Engineering from Arizona State University, Dec 2000 (3.8 GPA).
• Bachelor of Science with highest honors (summa cum laude) in Electrical Engineering from Arizona State University, May 1999 (3.96 GPA).

Work Experience:

Intel Corporation:

Software Enabling and Optimization Engineering Manager, June 2021 to present; Network Platforms Group; Chandler, Arizona.

Senior Software Platform Application Engineer, January 2011 to June 2021; Network Platforms Group; Chandler, Arizona.

• Customer support (engineer-to-engineer) and enabling for cryptography and compression software for our communications platforms
• Customer support (engineer-to-engineer) and enabling for our Media Software Development Kit
• Technical writing, usability testing, diagnostics, problem solving, and coding
• Technical training, including video development
• People management

Analog Engineer, August 2005 to December 2010; Electrical Design and Analysis / Packaging and Interconnects; Chandler, Arizona.

• Power integrity design and analysis for enterprise platforms
• Project management and oversight of supporting engineers
• Software engineering and application development for our power integrity analyses

Signal Integrity Engineer, May 2004 to August 2005; Signal Integrity Team / Packaging and Interconnects; Chandler, Arizona.

• Managed PCI-Express projects and analysis for various enterprise platforms

Package Design Engineer, January 2001 to May 2004; Substrate Design Engineering / Assembly Technology Development; Chandler, Arizona.

• Substrate Design Engineering Desktop/Chipsets Manager
• Responsible Engineer for various desktop and chipset packages
• Performed physical design, electromagnetic modeling, computer simulation, signal integrity, and power delivery optimization using novel methods and application of electromagnetic field solvers, circuit simulators, and transmission line theory
• Software engineering and application development for our power integrity analyses for desktop, enterprise, and mobile design teams

Mayo Foundation:

Engineering Co-op, Summers of 1997, 1999, 2000; Special Purpose Processor Development Group; Rochester, Minnesota.

• Performed verification and studies of the w-element model (HSPICE) and a PSPICE model developed at Arizona State University
• Software engineering and application development for computer simulation of transmission line models
• Developed mathematical methods, deembedding techniques, and automation to convert S-parameters to transmission line parameters (RLCG)

Arizona State University:

Undergraduate Research Assistant, August 1997 to July 1999; Electronics Packaging Lab; Tempe, Arizona.
Graduate Research Associate, August 1999 to May 2000.

• Computer simulation and electromagnetic modeling of transmission lines
• Developed an adaptive meshing scheme for improving Weeks’ method for computing frequency-dependent impedance of conductors
• Studied and characterized signal integrity problems with an SMA connector launch off of a printed circuit board
• Software engineering and application development for custom transmission line models

Selected Academic Awards:

• University Graduate Fellowship
• Distinguished Senior in Electrical Engineering
• National Science Foundation Graduate Fellowship Honorable Mention
• Goldwater Science and Engineering Scholarship

Skills:

• General: Application development, software engineering, programming, project management, MySQL, computer simulation, microwave circuit design, electromagnetic modeling, transmission line analysis, package design, simultaneous-switching noise, signal integrity, customer support, people management, video development, video editing
• Programming languages: C/C++, Java, VB, VBA, Perl, shell scripting, HTML, CSS, Python, PHP
• Software: Cadence tools (Advanced Package Designer (APD), Allegro), Ansoft tools (Q3D, HFSS), Matlab, SPICE, LaTeX, Framemaker, Kdenlive, Microsoft Office (Excel, PowerPoint, Word, Outlook, Project)
• Operating Systems: UNIX, Linux, Windows, FreeBSD

Publications:

• Xingling Zhou, Joel Auernheimer, George Pan, and Barry Gilbert: “An Improved SPICE Compatible Model for Multiconductor Transmission Lines.” Published in IEEE CEFC ’98 The Eighth Biennial IEEE Conference on Electromagnetic Field Computation, June 1-3, 1998 in Tucson, Arizona, p. 363. (Abstract)
• Joel A. Auernheimer, “Streamlined Methods for Power Delivery Simulations,” Design and Test Technology Conference (Intel internal conference), July 2002.
• Joel A. Auernheimer and Farzaneh Yahyaei-moayyed, “Efficient and Flexible Power Distribution System Design and Analysis,” Design and Test Technology Conference (Intel internal conference), July 2003.
• Joel A. Auernheimer, “New Methods for Power Distribution System Design and Analysis,” Electronic Components and Technology Conference, June 2004.
• Joel A. Auernheimer, “On the Efficient Creation and Manageability of SPICE Files,” Design and Test Technology Conference (Intel internal conference), July 2010.

Patents:

• 6 patents in the field of electronic packaging